Is advanced packaging in a new golden age? Almost everyone offering analysis on the IC industry thinks so (see here, here, here, here, as examples). Optimism abounds. Off-the-die interconnects for AI training are an increasingly important differentiator. Harvard Business School professors are waxing poetic about new advanced packaging facilities. Enterprising founders are deriving new laws to replace Moore's Law. Finally, companies and governments are all making big bets to reshore this part of the supply chain.
Over the last year, RCD Advisors has worked with several clients to help them address some part of the "new" advanced packaging opportunity. Each project was different, but all started from the same baseline assessment. These research posts are a conduit for sharing ideas with current and prospective clients. With this goal in mind, we offer the practice's starting point for approaching new business development in the post-Moore era of advanced packaging.
We focus on advanced packaging processes that enable high-density system-in-package (SiP). The scope includes wafer-level packaging, interposers, bridge chips, and 3D devices. For readers unfamiliar with these technologies, there are many well-written overviews. See here, here, or here for a few good examples.
It is also worth defining the end markets. We are specifically discussing advanced packaging for high-end CPUs, AI accelerators, and to a lesser extent, smartphone processors. These applications need the highest bandwidth between dies. They depend on SiP assembly to deliver differentiated performance. They're also the most lucrative. Over the last 12 months, the demand for AI processors has pushed processed semiconductor pricing to a record peak. Most of it is due to Nvidia's profits. But some of this value flows back to advanced packaging and wafer fabrication. And it looks like TSMC is trying to get a bigger piece of that pie.
The Intrinsic Value of Package Assembly
The history of advanced packaging as an investment isn't encouraging. The outsourced semiconductor assembly and test (OSAT) business has an average 9.1% return on invested capital (ROIC). If you adjust for intangibles (i.e., R&D, engineering, and marketing), the average ROIC only increases to 9.2% (link).
These two ratios say a lot about how much value package assembly creates in the IC supply chain. First, the ROIC is low compared to other parts of the value chain. Fabless suppliers and foundries command an 18-20% ROIC. The difference in returns suggests package assembly services have lower entry barriers and switching costs. Put another way, package assembly organizations work within a narrow economic moat. Second, most of the return is from hard assets. Those hard assets are the resources that allow fabless customers to outsource and make the "capex for opex" trade. The engineering content (intellectual property) doesn't significantly boost returns.
So, how do we reconcile the increasing importance of advanced SiP assembly with past financial performance? Where do the investment returns come from if interconnects are indeed more valuable in the post-Moore chiplet world? How do organizations capture that value? Let's explore these questions in the following few sections.
Slowing Moore's law
The common narrative behind the increasing importance of advanced packaging is that as Moore's law slows down, the only way to achieve higher functionality is to use more silicon (with chiplets). Those chiplets have to connect with advanced interconnects in the package. The assumption is that the cost of advanced package assembly will remain stable or decrease at a slower rate compared to the cost of maturing front-end wafer fabrication processes.
Intel CEO Pat Gelsinger has described this thinking many times over the last few years. In a recent IFS Direct Connect event, Mr. Gelsinger commented that CPU packaging has gone from 15% of the IC BOM costs five years ago to 35-40% today. Indeed, Intel is basing much of its comeback strategy on the "Systems Foundry" advantage provided by advanced packaging. Mr. Gelsinger is presumably using an example of silicon on trailing-edge fab processes with leading-edge (Foveros) advanced packaging.
As of today, Mr. Gelsinger's observation is more of an outlier than the norm. Most advanced packaging applications today use chips fabricated on the latest-generation front-end processes. In these applications, the silicon content is increasing as fast as (or faster than) the package assembly costs. The relative BOM cost contributions have, on average, tracked each other. In other words, advanced packaging costs have grown with the costs of front-end wafer fab processes. This is true for most of the leading-edge market.
Moreover, there are examples where the packaging assembly costs have decreased as a percentage of the BOM. For example, the latest AI (Blackwell) processor from Nvidia stitches together two die on the same TSMC 4NP process to roughly double the silicon content. Nvidia used bridge chips on an RDL (redistribution dielectric layer) organic substrate to stitch these devices together. This packaging technology is cheaper than the silicon interposer used in the previous generation (Hopper) processor. In this example, the silicon content increased (~2x die), and the packaging assembly content decreased.
It isn't clear whether advanced packaging will become the main innovation path as Moore's law slows. The two value chain steps are connected. Wafer fab technology tends to drive advanced packaging adoption. TSMC has cleverly linked the future innovation needed in advanced packaging to front-end wafer fab advancements. Some folks have used this chart to show that advanced packaging is an enabler. But it may be better to view it as “linked.”
The correlation makes sense because increasing transistor count drives higher off-die signal bandwidth, which then drives the need for advanced packaging. Even as it slows, Moore's law controls the adoption of more advanced packaging. We can drill down the correlation further to high-bandwidth memory technology roadmaps and the off-chip interconnects required for those interconnects (HBM4, HBM4E, HBM5, etc.).
Functionality Migration
SiP is becoming the new platform for electronic assembly. As a result, it is incorporating some functions that were once on the motherboard. For example, once on a motherboard, processor-to-processor interconnects are now more commonly on an interposer. Thermal management and co-packaged optics are other examples of functions moving onto the package.
Advanced packaging processes capture the added assembly content of this component migration from the board assembly. Processor-to-processor interconnects increase the interposer cost and (in theory) reduce the PCB motherboard cost. Some thermal management content shifts from the heat sink to the package heat spreader. Some of the costs of pluggable optical modules transfer to silicon photonic modules on the package.
Sometimes, there is a net cost savings at the system level (co-packaged optics). In some cases, there is a net cost increase (future use of diamond heat spreaders). Regardless, the margins of this added assembly are among the lowest in the electronics supply chain (EMS/ODM board assembly). So, the main point is that the migration of component technology from the PCB board to the package assembly will increase advanced packaging content. But it will probably also dilute margins.
Foundry Competitive Barriers
Advanced packaging is getting a boost in profitability/value from enhanced competitive barriers. Today, foundries (more specifically, TSMC) provide the most advanced packaging. The service is bundled with their front-end processes to lock in customers. Integration simplifies the back and front-end coordination, especially when accounting for known-good die. Finally, the profits from the higher-margin fab business can support advanced packaging development. TSMC's competitive advantage is its pipeline and as a result, commands approximately 80% of the SiP advanced packaging market today (excluding HBM 3D stacking).
Only a few foundries can afford the capital investments in EUV lithography (for the front end). That investment allows them to divert some returns into leading-edge package assembly capability that will lock in customers.
In addition to vertical integration, ecosystems also increase competitive barriers. Each foundry has its own design kits and ecosystem (3Dblox, 3DCode, CDXML, etc.), reinforcing customer “stickiness”. The switching costs will increase further as chip designers push the optimization boundaries from the die to the system (STCO).
The large fabless chip designers can circumvent this lock-in. They have the resources to engineer complete solutions internally without no any need to mix and match with external vendors or ecosystems. Smaller suppliers don't have that luxury. They are typically tethered with limited bargaining leverage.
It is a common refrain: chiplet technology needs open ecosystems for broader adoption. But there are disincentives for foundries to create one. Until that impasse is resolved, advanced packaging will only contribute higher returns to the leading foundries. And at least for external observers, those returns are blended with the returns on their front-end processes.
The Reshoring Trade
But there may be some chinks forming in these competitive barriers. In late November 2023, Amkor announced plans to construct a $2 billion advanced packaging facility in Peoria, Arizona. The facility is near TSMC's new US plant. Amkor, like TSMC, will likely receive funding from the US CHIPs Act.
Likewise, ASE is considering building an advanced packaging facility in Japan with the help of subsidies. This proposed plant will be located near a proposed new TSMC fab. Again, both companies are expected to receive subsidies from the Japanese government.
Silicon Box, a Singaporean startup OSAT, announced in March 2024 that they would make another $3.6Bn factory investment in Italy, taking advantage of the European CHIPS Act. Although there were no announcements to co-locate near a foundry, Europe has several IDMs that could capitalize on the re-shored capability.
In these examples, OSATs are globalizing their footprint to unlock business activity embedded in foundries and IDMs. The lower operating margins of the OSAT providers can at least partially offset the higher operating costs of running an advanced packaging facility in a higher-cost region (with the help of subsidies). Reshoring allows domestic fabless customers to trade the higher margins of foundry packaging services with lower-margin OSATs with higher-cost local facilities. And in some instances, the foundries are happy to offload those businesses to avoid eroding margins (link).
The lingering issue is sustainability. Subsidies to support reshoring are dwindling. The only way for advanced packaging processes to remain competitive in high-cost regions is through continued government support or customers committed to buying from those factories. In the US, government officials and industry leaders are already setting the stage for the former. Amkor worked with Apple to ensure it could secure the latter. (Could Nvidia’s advanced packaging supply be the next target for reshoring?).
Ultimately, this "reshoring trade" doesn't change the advanced packaging portion of the BOM. It is a trade. It lowers the overall margins of advanced packaging. But it also raises operational costs.
Broader Adoption
Reshoring could possibly be a catalyst for broader advanced packaging adoption. At least that is the narrative. As OSATs begin to win re-shored business, there will be more process providers that could potentially coalesce around a single ecosystem and lower switching costs from foundries. In addition, the cost pressures of the consumer and automotive sectors should motivate fabless suppliers to seek cost savings. This scenario, if it plays out as described, may offer an opportunity for OSATs to win business from foundries.
OSATs are well-positioned to capitalize on this transition for high-volume applications. However, they will take down the opportunity with the same financial metrics they have always achieved. The bottom line is that reshoring doesn't affect the content of advanced packaging in an IC BOM. It may rearrange the supply base, but ultimately, it will lower overall industry margins by transitioning from foundries to OSATs.
There have also been attempts by the US government to reshore advanced packaging for low-volume, high-mix applications. The most relevant program in the US is the Industrial Base and Sustainment (IBAS) Cornerstone program and its Reshore Ecosystem for Secure Heterogeneous Advanced Packaging Electronics (RESHAPE) awards. Skywater and DECA were awarded $120M to develop Fanout Wafer Level Packaging services to augment existing advanced packaging capability at the foundry in Florida.
The supply base for low-volume, high-mix SiP processes is still evolving. Early entrants are approaching the market by offering many process technologies to many customers. Costs are higher because of the higher engineering support required. In these sectors, advanced packaging content may indeed be rising as a percentage of the overall IC BOM. Moreover, the niche business model may also contribute to higher profits (value).
Even though it may not be a large market, the low-volume, high mix market could be lucrative. The winning formula is for process providers to scale up without adding more engineering overhead. Working with a single-process technology that can meet the needs of most applications is critical. In that regard, Fan Out processes seem like the most versatile approach.
Conclusion
Advanced packaging may be in a new golden age, but not for the reasons most people think. It isn't the slower innovation cycle of Moore's law driving advanced packaging value. It is primarily the competitive barriers erected by the major foundries. Moreover, as SiP is becoming the new platform for electronic assembly it will begin to absorb some low-margin board assembly value. Ultimately, its the bargaining leverage of foundries, and the added assembly migration, that could add to the top line market growth.
Reshoring complicates this landscape. Reshoring will mostly rearrange the supply base, while lowering industry margins and increasing operating costs. But as advanced packaging processes trickle down to lower volume applications, there are opportunities to increase content and profits for suppliers who can successfully streamline and “mass customize” operations.
Working within the constraints of this evolving market is minefield for new entrants, no matter where they sit in the value chain. Contact RCD Advisors if your organization is looking to exploit the opportunity for advanced packaging.
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